1. Field of the Invention
The present invention relates to a successive approximation analog/digital converter (ADC), and more particularly, to a successive approximation ADC allowing for an improvement in operating speed by reducing the time required for data conversion.
2. Description of the Related Art
Analog signals such as sounds or waves existing in the natural world are converted into digital signals through an analog/digital converter (ADC), and then the converted digital signals are used in digital devices such as televisions or cellular phones. With the current digitizing trend of many electronic devices, analog/digital conversion technology related to the interface of the analog and digital signal processing is becoming increasingly important.
With regard to such an ADC, a variety of technologies in many applications have been proposed and practically applied. Particularly, in wireless communication devices, ADCs require low power consumption in light of characteristics of wireless communication devices. Also, with increased interest in broadband communications, ADCs capable of achieving high-speed operation as well as low power dissipation are required.
Among a variety of ADCs, a successive approximation ADC has a relatively simple circuit structure relative to ADCs having different structures and is presented as a low power design. By applying time-interleaved technology to such a successive approximation ADC, it has been developed to allow the operating speed of the ADC to be enhanced by as much as an interleaving factor. Also, the development of semiconductor manufacturing process technology has made a contribution to the reduction of circuit line width, and thus the operating speed of the ADC has been enhanced. For this reason, a successive approximation ADC using the time-interleaved technology takes advantage of low power over existing ADCs with different structures and operates at a high speed, so it is known as an optimized structure in terms of power consumption and operating speed.
However, since such a successive approximation ADC converts analog signals into digital signals through a multi-stage comparison and approximation procedure, the conversion of input analog signals into digital signals can be a time-consuming process. That is, in the case of a general successive approximation ADC having an N-bit resolution, the time required for converting the data becomes the time of total N+1 clock cycles by adding the time of N clock cycles required for comparing N-times and that of 1 clock cycle required for analog signal sampling.
Therefore, in order to improve the operating speed of the successive approximation ADC, the reduction of clock cycles required for data conversion is required.